Analog and Mixed Signal Layout Engineer

Bengaluru · 5-10 years experience · Full-time · Onsite · Posted Oct 7, 2026

At a glance

At Lumilens, we’re building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. Our technology enables faster, cooler, and more efficient computing through cutting-edge optical solutions and high-performance connectivity IPs. If you’re driven by innovation and eager to shape the future of AI infrastructure, we invite you to join our world-class engineering team.

Lumilens is seeking an Analog and Mixed Signal Layout Engineer to play a key role in developing high-speed connectivity IPs using advanced semiconductor process technologies.

Design and implement complex analog, mixed-signal, and RF layouts for high-performance connectivity IPs, including floorplanning, device placement, and routing.
Work closely with circuit designers to translate schematics into robust physical implementations from floorplanning through tapeout.
Own physical verification and signoff closure including DRC, LVS, ERC, antenna, DFM, and EMIR.
Optimize layouts using extraction results to meet performance, matching, noise, and reliability targets.
Contribute to layout reviews and help drive effective layout methodologies and best practices.
Improve layout productivity and quality through automation, scripting, and AI-assisted workflows.
Develop high-performance connectivity IPs used in AI, networking, and next-generation compute systems.

BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or a related field
Hands-on experience with layouts for SerDes, data converters, clocking circuits, power management, transceiver building blocks, or related connectivity IPs.
Proven experience in full-custom layout and signoff including RC extraction, DRC, LVS, ERC, DFM, and EMIR.
Experience with advanced semiconductor technologies including CMOS, FinFET, BiCMOS, or SiGe.
Strong understanding of semiconductor process technologies, device physics, and layout-dependent effects.
Proficiency with Cadence Virtuoso and industry-standard EDA tools.
Experience leveraging automation, scripting, or AI-assisted methodologies to improve layout productivity and quality.
Solid understanding of layout techniques including matching, shielding, clock distribution, power planning, ESD protection, latch-up prevention, manufacturability, and reliability-aware design.
Demonstrated success delivering complex layouts through tapeout.
Ability to work effectively with globally distributed design, verification, CAD, and technology teams.

Exposure to silicon photonics, co-packaged optics (CPO), near-package optics (NPO), optical transceivers, or high-bandwidth connectivity solutions is a strong plus.