ASIC Design Engineer (Silicon Engineering)
Palo Alto · Irvine · Redmond, WA · 1+ years experience · Posted Oct 10, 2026
At a glance
- Experience
- 1+ years experience
- Location
- Palo Alto · Irvine · Redmond, WA
About the role
- SpaceX is seeking a motivated, proactive, and intellectually curious ASIC Design Engineer to develop cutting-edge next-generation FPGAs and ASICs.
- You will work alongside world-class cross-disciplinary teams to support space and ground infrastructures for the Starlink network.
Responsibilities
- Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog
- Optimize designs for power, performance and area
- Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
- Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
- Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification
- Collaborate with software engineers in developing production software for your designs
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
- Ability to work extended hours or weekends as needed for mission critical deadlines
- Applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State
Preferred qualifications
- ASIC/FPGA system integration experience
- Proficiency in Python, C/C++, and Bash
- Experience in designing DSP, digital communication system datapath blocks, and/or modem design
- Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
- Experience and understanding of AXI/AHB/APB protocols
- Strong foundation in electrical engineering fundamentals
- Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers
- Master’s in Electrical/Computer Engineering or related field
Benefits
- Long-term incentives in the form of company stock or long-term cash awards
- Potential discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks of paid vacation
- 10 or more paid holidays per year
Skills
- Verilog
- SystemVerilog
- VHDL
- Python
- C/C++
- Bash
- VCS
- Questa
- IES
- Spyglass
- Xilinx Vivado
- Altera Quartus II
Show all 15 skills
- AXI
- AHB
- APB
