Formal Verification Engineer
Santa Clara · Remote · North America · USD 100,000-500,000 · 6+ years experience · Remote · Posted Oct 5, 2026
At a glance
- Experience
- 6+ years experience
- Workplace
- Remote
- Location
- Santa Clara · Remote · North America
- Salary
- USD 100,000-500,000 · OTE
About the role
- The Formal Verification Engineer will ensure the correctness of next-generation high-performance RISC-V CPUs and AI compute platforms. This role involves using formal methods to prove complex hardware behavior and uncover corner cases that simulation may miss. You will collaborate with CPU architects and RTL designers to develop properties and build formal verification environments.
Responsibilities
- Use formal methods to prove complex hardware behavior
- Uncover corner cases that simulation may miss
- Develop properties, build formal verification environments, and analyze failures
- Work closely with CPU architects, RTL designers, and other DV engineers
- Drive issues to closure
- Apply formal techniques to challenging problems in modern processor design
Requirements
- 6+ years of experience in design verification, formal verification, or related RTL verification for CPUs, SoCs, ASICs, or complex digital designs
- Hands-on experience with formal verification methodologies and tools, including property checking, assertions, assumptions, constraints, and coverage analysis
- Strong SystemVerilog skills, including experience writing and debugging SVA
- Solid understanding of digital design and computer architecture
- Strong programming and scripting skills in Python, Tcl, C/C++
Benefits
- Highly competitive compensation package
- Variable compensation targets
Workplace
- Remote role based out of North America or Spain
Skills
- SystemVerilog
- SVA
- Python
- Tcl
- C
- C++
- Formal Verification
- RTL Verification
- RISC-V
