At a glance
- Location
- San Jose
About the role
- Astera Labs is seeking a Principal Digital Design Engineer to develop micro-architecture and front-end circuit design for high-performance network controllers.
- The role involves tasks such as RTL, synthesis, IP integration, and block-level verification.
Requirements
- Strong academic and technical background in electrical engineering
- A Bachelor’s degree in EE is required
- +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
- Entrepreneurial, open-mind behavior and can-do attitude
- Authorized to work in the US and start immediately
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
- Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
- Experience with Synopsys and/or Cadence digital design tools/flows
Preferred qualifications
- Master’s degree in EE
- Firmware development with C-language, scripting with Python or other equivalent programming languages
- Development/support for PCIe or Ethernet Switch products
Skills
- RTL
- PCI-Express
- Ualink
- Esun
- Ethernet
- Synopsys
- Cadence
- DFT
- UVM
- C
- Python
