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Principal Engineer, ASIC Design Verification

Samsung Semiconductor

San Jose · SSI San Jose · USD 219,000-351,000 · 20+ years experience · Full-time · Onsite · Posted Oct 6, 2026

At a glance

Experience
20+ years experience
Employment
Full-time
Workplace
Onsite
Location
San Jose · SSI San Jose
Salary
USD 219,000-351,000 · Base salary

About the role

  • The Principal Engineer, ASIC Design Verification will work within the DRAM Development Lab to verify modules and subsystems for AI accelerators. This role involves architecting test benches, defining verification strategies, and supporting post-silicon bring-up for memory and storage technologies.

Responsibilities

  • Participate in verification strategy and methodology definitions
  • Contribute in micro architecture specification and reviews
  • Responsible for the verification of modules/subsystems of AI accelerators
  • Architect test benches, create test plans, implement test bench components in UVM
  • Execute the verification per plan to the closure
  • Work closely with architects and design engineers to define verification requirements
  • Close functional and code coverage targets
  • Provide support in post silicon bring up and debug

Requirements

  • BE (MS preferred) in Computer/Electrical Engineering or Computer Science
  • Experience in UVM
  • Strong language skills including C++ and SystemVerilog
  • Experience in logic and SoC verification from planning to closure
  • Good understanding on verification flows and tools
  • Experience in UCIe, HBM controller, and Memory DFT

Preferred qualifications

  • Experience in DDR and Custom HBM and related IP level and/or SOC level verification
  • Experience and/or knowledge of emerging technologies (CXL, Computation in memory and storage, AI LLM accelerators) in server memory and storage systems
  • Highly motivated with good verbal and written communication skills
  • Creativity in problem solving
  • Inclusive, adapting style to diverse global norms
  • Avid learner approaching challenges with curiosity and resilience
  • Collaborative, building relationships and offering support

Benefits

  • Medical/Dental/Vision
  • 401k
  • Charitable giving match
  • 4+ weeks of paid time off per year
  • Holidays and sick leave
  • Stipend for fertility care or adoption
  • Caregiver support
  • Medical travel support
  • On-demand apps and free confidential therapy sessions
  • Onsite Café and gym

Workplace

  • Daily onsite presence in San Jose HQ or Folsom location 5 days a week

Skills

  • UVM
  • C++
  • SystemVerilog
  • SoC Verification
  • UCIe
  • HBM Controller
  • Memory DFT
  • DDR
  • CXL
  • AI LLM Accelerators

Samsung Semiconductor

Principal Engineer, ASIC Design Verification

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