Principal Physical Design CAD Engineer
Haifa District · Haifa · Tel Aviv · 3+ years experience · Posted Oct 11, 2026
At a glance
- Experience
- 3+ years experience
- Location
- Haifa District · Haifa · Tel Aviv
About the role
- Astera Labs is seeking a Principal Physical Design CAD Engineer to join its strategic R&D center in Israel and drive the development of complex semiconductor chips for AI infrastructure.
- This role involves implementing parasitic extraction (PEX) methodologies and flows for high-speed designs from RTL to GDSII.
- As a foundational team member, you will combine strong physical design knowledge with modern automation and GenAI-based methodologies.
Responsibilities
- Develop and support physical design CAD flows using industry-standard EDA tools
- Build automation infrastructure for implementation, analysis, reporting, and debug
- Support design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification
- Create scripts and utilities to improve productivity, quality of results, and flow robustness
- Support and enhance flows based on Synopsys Fusion Compiler
- Explore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity
- Analyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues
Requirements
- At least 3 years of experience in Physical Design, CAD, or implementation methodology
- Strong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification
- Hands-on experience with Synopsys Fusion Compiler
- Experience with scripting languages such as Tcl, Python
- Ability to develop automation around EDA tools and large-scale design flows
- Good understanding of timing, power, congestion, floorplanning, and QoR analysis
- Strong debugging and problem-solving skills
- Ability to work closely with multiple engineering teams and support complex design environments
- High motivation to learn and apply GenAI technologies in semiconductor design flows.
Preferred qualifications
- Experience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar
- Knowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows
- Experience building dashboards, regression systems, flow checkers, or automated report analyzers
- Familiarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools
- Experience with Git, CI/CD, databases, or cloud-based compute environments
Skills
- Tcl
- Python
- Synopsys Fusion Compiler
- PrimeTime
- StarRC
- ICC2
- Innovus
- Voltus
- RedHawk
- Calibre
- Git
- CI/CD
