Principal Physical Design Engineer

Singapore · Singapore City · 5-10 years experience · Posted Oct 13, 2026

At a glance

We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes.

Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes.
Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
Apply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
Work on key physical design areas including EM/IR analysis and power grid optimization, congestion analysis and mitigation, clock skew optimization and clock quality improvement, and RC extraction-aware placement and routing.
Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
Support floorplan development and chip partitioning for high-speed transceiver designs.
Perform ECO implementation and assist with tapeout signoff activities.
Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.
Use industry-standard tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre for implementation and signoff.
Develop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity.

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
5-10 years of experience in physical design, preferably with advanced technology nodes.
Strong experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
Signoff checks such as DRC, LVS, ANT, and ERC, along with debugging.
Timing closure support in collaboration with STA teams.
Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
Experience working on high-frequency datapath and DSP-related designs.
Solid scripting skills for automation and productivity enhancement.
Good problem-solving skills and the ability to work effectively in cross-functional teams.