Principal SerDes Bring-up Validation Engineer

San Jose · USD 185,000-240,000 · 8-12 years experience · Posted Oct 5, 2026

At a glance

Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer to join a cutting-edge mixed-signal design team and lead end-to-end post-silicon bring-up, validation, and characterization.
You will own bring-up and characterization strategies from the ground up, translating design and product requirements into measurable test objectives, pass/fail criteria, and schedules, and driving hands-on lab work to verify silicon against specification and performance targets.

Design, develop, and execute bring-up plans, owning end-to-end post-silicon bring up and characterization strategies.
Drive design reviews and specification alignment by participating in architecture and design-spec reviews to ensure testability.
Lead hands-on test execution and bring-up, performing silicon block level bring-up, functional and parametric testing, interop checks, and performance benchmarking.
Build and maintain automation frameworks by developing scalable test automation, data capture, and analysis pipelines.
Debug and optimize system performance by diagnosing complex failures and performance bottlenecks across analog, digital, firmware, and protocol layers.
Root-cause cross-domain failures to circuit, package, firmware, or protocol interactions using lab measurements and waveform analysis.
Collaborate with cross-functional teams including mixed-signal design, firmware, system engineering, and manufacturing.
Document findings and improve methodologies by producing clear debug reports, formal characterization summaries, and recommendations.
Develop test software and platform integrations by writing Python test scripts and control interfaces.
Measure and communicate impact by defining key validation metrics, tracking coverage and defect trends, and presenting data-driven conclusions.

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation with industry instruments such as protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers, with a strong understanding of the physical layer.
Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization).
Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.
Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.

MS or PhD in Electrical Engineering or a related field.
Hands-on proficiency with signal integrity test equipment and methodologies and experience designing and debugging lab characterization and demo boards.
Working knowledge of IEEE 802.3 Ethernet standards and experience validating Ethernet PHYs, link training, auto-negotiation, and compliance across speeds and media types.
Practical understanding of serial interfaces such as I2C, I3C, SPI, and UART for device bring-up, firmware interaction, and system integration.
Proven ability to translate SI/PI simulation results into testable lab plans and document findings that drive design or process improvements.

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