Senior Analog Mixed-Signal IC Layout Engineer
Singapore · Singapore City · Posted Oct 13, 2026
At a glance
- Location
- Singapore · Singapore City
About the role
- Astera Labs is seeking a Senior Analog Mixed-Signal IC Layout Engineer to join the ASIC team in Singapore City.
- The role involves working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes.
Responsibilities
- Design and/or verification of blocks using leading edge methodology and tools.
Requirements
- Pursuing BS or MS in EE/CS or related fields.
- Hardware engineering background with an emphasis in VLSI or Computer Architecture.
- Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.
- Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
- Familiarity with verification methodologies like UVM, functional coverage, assertions.
- Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.
Preferred qualifications
- Real-world design and/or verification in Verilog/System Verilog.
- Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
- Familiarity with Synopsys EDA tools.
Skills
- Verilog
- System Verilog
- UVM
- Python
- Perl
- C
- C++
- Synopsys EDA Tools
- PCIe
- DDR
- HBM
- Serdes
