At a glance
- Location
- San Jose
About the role
- Astera Labs is seeking a Senior Digital Design Engineer to develop micro-architecture and implement front-end circuit design for high-performance network controllers.
Requirements
- A Bachelor's degree in EE is required
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks
- Entrepreneurial, open-mind behavior and can-do attitude
- Authorized to work in the US and start immediately
- Hands-on experience with high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design skill – architecture, RTL, simulations and synthesis
- Experience with Synopsys and/or Cadence digital design tools/flows
- Knowledge of design for test (DFT)
- Familiarity with UVM based design verification
- Silicon bring-up and debug experience
Preferred qualifications
- Master's degree in EE
- Knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
- Scripting with Python or other equivalent programming languages
- Development/support for PCIe or Ethernet Switch products
Skills
- RTL
- PCI-Express
- Ualink
- Esun
- Ethernet
- Synopsys
- Cadence
- DFT
- UVM
- Python
