Senior FPGA Verification Engineer
Goleta · Waltham, MA (WMA-01) · USD 191,000-253,000 · 8+ years experience · Full-time · Posted Sep 24, 2026
At a glance
- Experience
- 8+ years experience
- Employment
- Full-time
- Location
- Goleta · Waltham, MA (WMA-01)
- Salary
- USD 191,000-253,000 · Base salary
About the role
- The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines.
- In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products.
Responsibilities
- Verification environment architecture and design using tools like SystemVerilog or OVM/UVM
- Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
- Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
- Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
- Contribute to engineering estimates for new program pursuits.
- Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status
Requirements
- A Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
- 8+ years of experience developing HDL firmware for FPGA devices
- Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
- Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
- Experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)
- Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
- Eligible to obtain and maintain an active U.S. Secret security clearance
Preferred qualifications
- Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.
- Proficiency with Unix/Linux environments, scripting or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
Benefits
- Highly competitive equity grants included in the majority of full time offers
- Top-tier benefits for full-time employees supporting health, recovery, and whatever comes next
Skills
- SystemVerilog
- OVM
- UVM
- VHDL
- Verilog
- Git
- Subversion
- C
- C++
- Python
- Perl
- QuestaSim
Show all 15 skills
- Synplify
- Quartus
- Vivado
