Sr. ASIC Design Engineer (Silicon Engineering)
Palo Alto · Austin - 800 · Irvine · Palo Alto - 1200 · Redmond, WA · USD 175,000-280,000 · 5+ years experience · Posted Oct 10, 2026
At a glance
- Experience
- 5+ years experience
- Location
- Palo Alto · Austin - 800 · Irvine · Palo Alto - 1200 · Redmond, WA
- Salary
- USD 175,000-280,000 · Base salary
About the role
- The Sr. RTL Design Engineer will develop cutting-edge next-generation ASICs for deployment in space and ground infrastructures. This role involves working with cross-disciplinary teams to define micro-architecture and deliver fully verified, synthesis-ready designs for the Starlink network.
Responsibilities
- Evaluate architectural trade-offs based on features, performance requirements and system limitations
- Define micro-architecture
- Implement the RTL in Verilog/System Verilog
- Integrate RTL in top level
- Deliver fully verified, synthesis/timing clean design
- Work closely with verification team to ensure design coverage
- Provide timing constraints for IPs
- Support the physical implementation team with synthesis, timing closure, and formality checks
- Participate in silicon bring-up and validation
Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
- Must be a U.S. citizen, lawful permanent resident, refugee, or asylee to conform to U.S. Government export regulations
Preferred qualifications
- Ability to solve complex problems including clock domain crossings and power optimization
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols (e.g. AXI, AHB, etc.)
- Experience with high speed and low power design techniques
- Scripting skills (e.g. Python, etc.)
- Experience with EDA tools such as HDL simulators and HDL Lint tools
- Team-player, can-do attitude and ability to work well in a group environment
Benefits
- Long-term incentives (company stock or long-term cash awards)
- Discretionary bonuses
- Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short and long-term disability insurance
- Life insurance
- Paid parental leave
- 3 weeks of paid vacation
- 10 or more paid holidays per year
Skills
- Verilog
- System Verilog
- AXI
- AHB
- Python
- HDL Simulators
- HDL Lint Tools
