Staff HSIO Digital & Mixed Signal Design Engineer
San Jose · SSI San Jose · USD 163,000-253,000 · 3+ years experience · Full-time · Onsite · Posted Oct 13, 2026
At a glance
- Experience
- 3+ years experience
- Employment
- Full-time
- Workplace
- Onsite
- Location
- San Jose · SSI San Jose
- Salary
- USD 163,000-253,000 · Base salary
About the role
- This team is focused on next-generation HSIO (High-Speed I/O) design for Samsung’s AI production platforms.
- Ideal candidates will have 3+ years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies.
- Candidates are expected to have a strong understanding of the end-to-end digital design flow and the ability to collaborate effectively with system and analog teams.
Responsibilities
- BS in Electrical Engineering with 10+ years of experience or MS in Electrical Engineering with 8+ years of experience or PhD in Electrical Engineering with 5+ years of experience
- Hands-on experience with HSIO PHY IP (e.g., UCIe, BOW, PCIe)
- Deep understanding of high-speed serial interconnect protocols and associated design trade-offs
- Strong understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
- Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs
Requirements
- Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link
- Knowledge of Design for Testability (DFT) methodologies and flows
- Familiarity with Ethernet PMA / PMD / PCS layers
Benefits
- Medical/Dental/Vision/401k
- Charitable giving match
- 4+ weeks of paid time off a year, plus holidays and sick leave
- Stipend for fertility care or adoption, caregiver support, and medical travel support
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym, plus virtual classes
Workplace
- Working onsite at our San Jose headquarters
Skills
- UCIe
- BOW
- PCIe
- AXI
- CHI
- CXS.B
- CXL
- UA-Link
- Ethernet PMA
- PMD
- PCS
