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Teach Lead Physical Design Engineer

Astera Labs

Singapore · Singapore City · 5+ years experience · Posted Oct 13, 2026

At a glance

Experience
5+ years experience
Location
Singapore · Singapore City

About the role

  • Astera Labs is seeking a Senior Physical Design Engineer to join their high-performance design team.
  • The role focuses on next-generation transceiver IPs targeting TSMC 3nm and other advanced technology nodes.

Responsibilities

  • Perform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification.
  • Collaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.
  • Apply advanced physical design techniques for multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.
  • Conduct EM/IR analysis and power grid optimization.
  • Perform congestion analysis and mitigation.
  • Optimize clock skew and improve clock quality.
  • Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
  • Support floorplan development and chip partitioning for high-speed transceiver designs.
  • Perform ECO implementation and assist with tapeout signoff activities.
  • Ensure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
  • 5+ years of experience in physical design, preferably with advanced technology nodes.
  • Strong experience with floorplanning, placement, CTS, routing, and IR drop mitigation.
  • Experience with signoff checks such as DRC, LVS, ANT, and ERC, along with debugging.
  • Experience with timing closure support in collaboration with STA teams.
  • Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus.
  • Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.
  • Experience working on high-frequency datapath and DSP-related designs.
  • Solid scripting skills for automation and productivity enhancement.
  • Good problem-solving skills and the ability to work effectively in cross-functional teams.

Skills

  • TSMC 3nm
  • ICC2
  • Innovus
  • Voltus
  • RedHawk
  • Calibre
  • Tcl
  • Python
  • Perl
  • SerDes
  • SoC
  • DSP

Astera Labs

Teach Lead Physical Design Engineer

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