Principal Engineer, Architecture & Performance Research for Data Center and Agentic AI CPU
San Jose · SSI San Jose · USD 219,000-351,000 · 5+ years experience · Full-time · Onsite · Posted Oct 2, 2026
At a glance
- Experience
- 5+ years experience
- Employment
- Full-time
- Workplace
- Onsite
- Location
- San Jose · SSI San Jose
- Salary
- USD 219,000-351,000 · Base salary
About the role
- The Architecture Research Lab at Samsung Semiconductor is seeking a Principal Engineer to define the architectural vision and performance direction for next-generation RISC-V CPU platforms.
- This role focuses on emerging data center and agentic AI workloads, utilizing AI-driven methodologies to accelerate architectural exploration and silicon validation.
- The position involves broad technical ownership, spanning from workload analysis and microarchitectural innovation to implementation and silicon validation.
Responsibilities
- Define the application-specialization direction for next-generation CPU cores, including agentic AI and memory-centric architectures.
- Lead the overall microarchitectural vision and strategy.
- Lead end-to-end performance analysis using architectural simulators and RTL.
- Translate workload characterization and performance insights into architectural requirements and long-term design direction.
- Drive architecture-to-implementation alignment with design teams to ensure architectural intent is carried through RTL and silicon.
- Mentor Senior and Staff engineers and provide technical leadership across multiple projects and architectural domains.
- Drive research and technical contributions leading to patents and publications.
Requirements
- Master’s degree in Computer Engineering, Computer Science, or a related field with 18+ years of relevant experience, or PhD with 15+ years of relevant experience.
- 5+ years of experience in CPU microarchitecture, architecture research, or performance engineering.
- Extensive experience designing and evaluating high-performance CPU architectures, including RISC-V, ARM, or x86 cores.
- Proven ability to use quantitative performance analysis and modeling to identify architectural opportunities and influence major microarchitectural decisions.
- Deep expertise in at least one major microarchitectural domain (Front-end, Mid-end, or Back-end).
- Hands-on experience building, extending, and applying architectural simulators and performance models, such as gem5.
- Strong programming skills in C/C++ and Python.
Preferred qualifications
- Experience defining or influencing CPU architecture for emerging workloads, particularly AI/ML, agentic AI, or data center applications.
- Experience with AI-driven architecture and design methodologies.
- Strong perspective on memory-centric architectures and CPU-memory co-design.
- Experience driving system-level PPA trade-offs.
- Experience taking architectural concepts through RTL implementation, tape-out, and silicon validation.
- Experience leading cross-functional architecture initiatives.
- Track record of impactful architectural innovation through patents, publications, or deployed products.
Benefits
- Medical, Dental, and Vision insurance
- 401k
- Charitable giving match
- 4+ weeks of paid time off per year
- Holidays and sick leave
- Stipend for fertility care or adoption
- Medical travel support
- Virtual vet care
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym
Workplace
- Daily onsite presence at the San Jose office is required.
Skills
- RISC-V
- ARM
- X86
- GPU
- NPU
- Gem5
- C
- C++
- Python
- RTL
- Microarchitecture
