At a glance
- Location
- Ahmedabad, Gujarat · Ahmedabad
About the role
- Astera Labs is seeking a Principal Physical Design Engineer to support or develop complex SoC/silicon products for Server, Storage, and/or Networking applications.
- The role involves full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
Responsibilities
- Prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
- Drive multiple complex designs to production with full chip or block level ownership from architecture to GDSII
Requirements
- Bachelor's degree in EE / Computer
- ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
- Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less
- Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level
- Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
- Experience with Cadence and/or Synopsys physical design tools/flows
- Familiarity and working knowledge of System Verilog/Verilog
- Experience with DFT tools and techniques
- Experience in working with IP vendors for both RTL and hard-mac blocks
- Good scripting skills in python or Perl
Preferred qualifications
- A Master's degree in EE / Computer
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
- Familiarity with DFT test coverage and debug
- Familiarity with ECO methodologies and tools
Skills
- System Verilog
- Verilog
- Python
- Perl
- Cadence
- Synopsys
