Principal Verification Engineer
San Jose · USD 185,000-230,000 · 8+ years experience · Posted Sep 29, 2026
At a glance
- Experience
- 8+ years experience
- Location
- San Jose
- Salary
- USD 185,000-230,000
About the role
- Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs.
- This role involves full lifecycle verification—from planning and test development to debugging and coverage closure—contributing to the success of cutting-edge SoC designs.
Responsibilities
- Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
- Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
- Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
- Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
- Work with RTL designers to troubleshoot and resolve design issues.
- Drive verification strategy and methodology for SoCs in server and networking applications.
Requirements
- Bachelor’s degree in Electrical Engineering (Master’s preferred).
- 8+ years of experience in SoC verification, particularly for server and networking applications.
- Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.
- Proficiency with industry-standard simulators, version control, and regression systems.
- Strong debugging and coverage analysis skills.
- Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
- Familiarity with verification of switching architectures, including packet processing and forwarding engines.
- Excellent communication skills and ability to work independently with minimal supervision.
Preferred qualifications
- Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
- Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
- Knowledge of Ethernet/PCIe switching and central buffer architectures.
- Experience with emulation platforms and hardware-software co-verification
Benefits
- Discretionary bonus
- Incentives
- Benefits
Skills
- SystemVerilog
- UVM
- C/C++
- Python
- PCIe
- Ethernet
- InfiniBand
