Staff Engineer, SRAM Circuit Design
San Jose · SSI San Jose · USD 163,000-253,000 · 8+ years experience · Full-time · Onsite · Posted Oct 15, 2026
At a glance
- Experience
- 8+ years experience
- Employment
- Full-time
- Workplace
- Onsite
- Location
- San Jose · SSI San Jose
- Salary
- USD 163,000-253,000 · Base salary
About the role
- We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions.
- In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products.
- Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.
Responsibilities
- Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
- Optimize SRAM designs for performance, power and area (PPA) and yield.
- Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
- Evaluate trade-offs between speed, power, and area to meet design targets.
- Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
- Work with product and test engineers to develop test plans and support silicon bring-up.
- Mentor Junior engineers, providing guidance on SRAM design techniques and best practices.
- Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance.
- Contribute to patents, technical papers, or industry conferences to advance SRAM technology.
Requirements
- Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
- Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.).
- Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
- Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
- Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
- Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
- Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams.
Benefits
- Medical/Dental/Vision/401k
- Charitable giving match
- 4+ weeks of paid time off a year, plus holidays and sick leave
- Stipend for fertility care or adoption, caregiver support, and medical travel support
- On-demand apps and free confidential therapy sessions
- Onsite Café and gym, plus virtual classes
- Flexible environment
Skills
- HSPICE
- Finesim
- Cadence Spectre
- DRC
- LVS
- Cadence Virtuoso
- Python
- Perl
- TCL