Tech Lead Engineer, Design Verification
San Jose · USD 175,500-195,000 · 5-8 years experience · Posted Sep 28, 2026
At a glance
- Experience
- 5-8 years experience
- Location
- San Jose
- Salary
- USD 175,500-195,000
About the role
- The Tech Lead Engineer, Design Verification will define and deliver verification strategies for next-generation connectivity silicon supporting rack-scale AI infrastructure.
- This role involves partnering with RTL, architecture, firmware, and post-silicon teams to verify complex switching behavior across high-bandwidth protocols.
Responsibilities
- Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements.
- Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality.
- Review designs and verification plans with architecture and RTL teams to identify corner cases.
- Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics.
- Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models.
- Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCIe behavior.
- Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration.
- Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones.
- Develop regression strategies and automation to improve test quality, turnaround time, and failure triage.
- Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 5–8 years of experience in design verification for complex ASICs or SoCs.
- Hands-on experience with SystemVerilog and UVM-based verification environments.
- Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
- Familiarity with simulation, waveform-debug, regression, and coverage tools.
- Strong technical leadership, debugging, communication, and collaboration skills.
Preferred qualifications
- Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience verifying PCIe, UALink, UCIe, or other high-speed connectivity and switching protocols.
- Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
- Experience with Python, PowerShell, or Tcl for verification automation and regression infrastructure.
- Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity.
Benefits
- Salary range of $175,500 to $195,000
- Eligible for discretionary bonus
- Eligible for incentives
Skills
- SystemVerilog
- UVM
- PCIe
- UALink
- UCIe
- Python
- PowerShell
- Tcl
- Formal Verification
- Emulation
