Principal / Senior Principal Electrical Design Engineer
San Jose · USD 185,000-240,000 · 12+ years experience · Posted Oct 19, 2026
At a glance
- Experience
- 12+ years experience
- Location
- San Jose
- Salary
- USD 185,000-240,000 · Base salary
About the role
- Astera Labs is seeking a Principal Electrical Design Engineer to define and drive the architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms.
- This role encompasses complex hardware systems including chassis boards, NIC cards, PCIe Gen6 platforms, and 800G Ethernet products.
- This is a principal-level technical leadership role requiring deep domain expertise, strategic vision, and organizational influence.
Responsibilities
- Define and own the board-level hardware architecture and technical roadmap across multiple product lines and platform generations.
- Establish design standards, methodologies, and best practices that scale across the hardware engineering organization.
- Drive architectural tradeoff decisions for complex multi-layer PCBs integrating high-speed digital, analog, and mixed-signal circuitry, balancing performance, cost, schedule, and manufacturability.
- Get involved and drive discussions on stack-up strategy, impedance optimization and other SI relates development work.
- Own power delivery architecture strategy including multi-rail regulation topologies, advanced sequencing schemes, transient response optimization, protection philosophies, and power budgeting across platform generations.
- Define and evolve hardware implementation strategies for management and control interfaces such as I2C, SPI, GPIO, MDIO, and debug and observability architectures.
- Own schematic capture and board-level design for complex multi-layer PCBs with high-speed digital, analog, and mixed-signal circuitry.
- Serve as the technical authority for board-level hardware development across high-performance server and connectivity platforms, including NIC cards, PCIe add-in cards, and chassis-integrated hardware.
- Define and own the bring-up and validation strategy for new hardware platforms, establishing frameworks that improve first-pass success rates across the organization.
- Mentor and develop senior and lead engineers, raising the technical bar across the hardware engineering team.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or a closely related field
- 12+ years of progressive hardware design experience with deep expertise in board-level electrical engineering and demonstrated technical leadership across multiple product generations
- Extensive track record of architecting and delivering production hardware for server, networking, storage, or high-performance compute systems at scale
- Expert-level experience with high-speed SerDes-based systems supporting Ethernet, PCIe, or related protocols; deep hands-on experience with PCIe Gen5/Gen6 and 400G/800G Ethernet system design
- Expert understanding of signal integrity fundamentals including impedance control, differential pair routing, channel loss optimization, crosstalk mitigation, and layout review for high-speed interfaces
- Expert power integrity and PDN design knowledge including advanced sequencing, decoupling strategies, transient response optimization, and power architecture tradeoffs at system level
- Mastery of industry-standard schematic capture and PCB design and review tools such as Cadence Allegro or OrCAD
- Proven track record leading hardware bring-up and debug of complex platforms using oscilloscopes, protocol analyzers, and advanced lab instrumentation
- Demonstrated ability to lead cross-functional teams and influence technical direction across organizational boundaries from architecture through validation and production
- Strong track record of mentoring engineers and elevating team capabilities
Preferred qualifications
- Experience defining architecture for NIC cards, accelerator cards, or other PCIe add-in card platforms across multiple generations
- Experience leading server chassis or system board design programs in dense, thermally constrained, high-availability environments
- Deep expertise with 800G Ethernet and emerging 1.6T electrical interfaces and system integration challenges
- Experience architecting solutions using retimers, redrivers, advanced clocking architectures, and high-speed interconnect subsystems
- Expertise in compliance and validation workflows for PCIe and Ethernet platforms, including contributions to industry specifications or standards bodies
- Experience driving contract manufacturer relationships, production ramp strategies, and yield optimization for complex hardware products
- Scripting and automation proficiency in Python or similar languages for lab automation, measurement analysis, hardware characterization workflows, and design flow optimization
- Experience influencing product strategy and roadmap decisions at the organizational level
Skills
- Cadence Allegro
- OrCAD
- Python
- PCIe Gen5/Gen6
- 400G/800G Ethernet
- SerDes
- I2C
- SPI
- GPIO
- MDIO
