Tech Lead, Digital Design Engineer
San Jose · USD 175,500-195,000 · 5-8 years experience · Posted Sep 28, 2026
At a glance
- Experience
- 5-8 years experience
- Location
- San Jose
- Salary
- USD 175,500-195,000
About the role
- Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure.
- You will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.
Responsibilities
- Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
- Develop front-end design solutions for high-performance networking and server connectivity applications.
- Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
- Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
- Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
- Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
- Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
- Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
- Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.
Requirements
- Bachelor’s degree in Electrical Engineering or a related field.
- 5–8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
- Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
- Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
- Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.
- Authorized to work in the United States.
Preferred qualifications
- Master’s degree in Electrical Engineering or a related field.
- Experience developing or supporting PCIe or Ethernet switch products.
- Familiarity with UVM-based design verification and coverage-driven debug.
- Silicon bring-up and debug experience in small-geometry CMOS technologies at 28nm or below.
- Scripting experience with Python or comparable programming languages, along with a collaborative, customer-focused approach.
Benefits
- Discretionary bonus
- Incentives
- Benefits
Skills
- RTL
- Synopsys
- Cadence
- UVM
- Python
- PCIe
- Ethernet
- UALink
- UCI
- ESUN
